B.1_Lot1_Digital design for floorplanning

rformance computing accelerators will be developed as a System on Chip in 12 nm silicon technology. In BCDC platform SoCs for industrial use cases are developed and in TrEB SoCs with security and safety functionalities both in 22 FDSOI technology.

The division SSE of Fraunhofer IIS is currently looking for contractors who can provide services as digital IC-design backend experts as part of the "TrEB, STX and BCDC" projects. In STXMOD the next generation of high pe