Closed
Verification platform for emulation of HDL designs using FPGAs
Deadline:28 Mar 2025
Tender information
TED EUErlangen, Germany
- Type
- 16
- Procedure
- open
- Ref. number
- 124735-2025
- CPV
- 48219100
Delivery of a FPGA-based verification platform consisting of a central FPGA platform, casing, software and support