Verification platform for emulation of HDL designs using FPGAs
Deadline:28 Mar 2025, 16:00 CET
Tender information
DE_BKMSErlangen, Germany
- Type
- goods (tender)
- Procedure
- Open
- Ref. number
- 29c48dfb-6d05-487a-81bc-2efb44614c27
- CPV
- 30200000
Delivery of a FPGA-based verification platform consisting of a central FPGA platform, casing, software and support